IOP-16 Performance
Revision as of 15:53, 19 April 2022 by Blwikiadmin (talk | contribs)
"Good enough" performance
- FPGA clock = 50 MHz
- High enough IOP-16 Performance - 12.5 MIPS
- 4 of 50 MHz FPGA clocks
- 2-bit Grey-code counter
Peripheral Strobes
- 1 clock wide write strobes
- 2 clock wide read strobes
