R32V2020 Assembler

Assembler

The assembler allows easy updates to the opcodes by reading the opcode table every time the assembler itself is run.

Programmer's Reference Card

Running the Assembler

python assembler.py <path_to_assembly_file.asm>

• Creates file_ins.HEX and file_dat.HEX files
  • file_ins.HEX - Instruction ROM HEX file
  • file_dat.HEX - Data RAM HEX file

Run without a specified file

python.exe assembler.py
Usage: python assembler.py <input assembly>
 

VHDL Opcode Constants Generator

• The assembler contains a helper function to make an file with VHDL opcode CONSTANTs
  • This helps keep the VHDL code in sync with the ops.csv file
• Used in OpCodeDecoder.vhd
• To generate the VHDL table of constants run

python assembler.py --gen-constants
 

• Result is <a href="https://raw.githubusercontent.com/douggilliland/R32V2020/master/Assembler/OpCodeConstants.vhd">here</a>:

constant NOP_OP : std_Logic_Vector(7 downto 0) := "00000000";
constant HCF_OP : std_Logic_Vector(7 downto 0) := "00000001";
constant ADD_OP : std_Logic_Vector(7 downto 0) := "00100000";
constant MUL_OP : std_Logic_Vector(7 downto 0) := "00100001";
constant OR_OP : std_Logic_Vector(7 downto 0) := "00100010";
...

Updating Opcodes

• Update opcode.csv
• Generate the VHDL table of constants (as above)
• Replace the constants table inside the file OpCodeDecoder.vhd

Assembly Language Syntax

Simple example

label:
  ADD r10,r9,r8
 

• Adds r8 plus r9 and stores the result in register r10
• label is optional

Branch example

label:
  ADD r10,r9,r8
  BRA label
 

• Same as previous example with a BRanch Always back to label

Data File Format

Numerical constants

nums1:  .LONG 0x12345678,0xffff00000,
nums2:  .SHORT 0xff00,0x4321
nums3:  .BYTE 0x55,0xde,0xbe,0xef,0x99

Strings

hi: .string "I have a comment after" ; I am that comment
hi2: .string "Look out for ; character"
empty: .string "foobar"
empty2: .string "Programmers like to say \"Hello world\""
empty3: .string "foobar,spameggs"

Updating Opcodes

• Modify `ops.csv` to add or change any operations.

ops.csv file

• The assembler is table driven from the ops.csv file
  • `ops.csv` file contains the opcode encoding (opcode bits and fields)
  • File is a subset (albeit not proper subset due to extra fields) of the opcode spreadsheet (R32V2020.xlsx)
  • This allows opcodes to be created/changed/deleted without affecting the assembler

Fields in `ops.csv`

Category,Form,Desciption,Opcode,D31,..,D00,,

• Category is the text version of the first three bits of the opcode field
  • Not used by the assembler
• Form is the encoding of the other field bits

  'ADDR',
  'ADDR_R7_DEST',
  'BIN_CMP',
  'BIN_DEST',
  'IMM_DEST',
  'NO_ARGS',
  'R4_DEST',
  'R5_DEST',
  'R6_DEST',
  'UN_DEST',
  'BIN_R1_DEST',
  'UN_R1_DEST',
  'UN_R4_DEST',
  'UN_R5_DEST',
  'UN_R6_DEST'

Running Assembler Tests

• To run the "end-to-end" tests, from a bash prompt (e.g. Git BASH) run

./tests/run.sh
 

• To run the unit tests, run

python assemblerSpecs.py