R32V2020 Instruction Set

From Land Boards Wiki
Jump to navigation Jump to search

Programmer's Reference Card

Contents

R32V2020 Instruction Set[edit]

  • All opcodes are 8-bits
  • There are seven opcode classes
    • The opcode class is encoded in the top three bits of the instruction
  • The specific opcode within the class is the next five bits

Opcode Classes[edit]

The opcode classes are:

  • System
  • ALU
  • Immediate
  • Load/Store
  • Peripheral
  • Stack
  • Flow Control

System Opcodes[edit]

NOP - NO Operation[edit]

  • Performs a no operation
  • Does not change Condition Codes
  • Does not change the Register File contents (other than advancing the PC)
  • May end up being used prior to conditional branches as the pipelined is developed
  • Syntax
  nop

HCF - Halt and Catch Fire[edit]

  • Causes the PC to stay at the current address
  • Can only be cleared by a reset or power cycling of the target hardware
  • Syntax
  hcf

ALU Operations[edit]

ADD - Add two registers[edit]

  • Add two registers and store in a third
  • The three registers can be any register (even the same register)
  • Sets the Condition Code Register bits
  • Can be used with r0 to set designation register to zero
    • ex: add r8,r0,r0 ; sets r8 = 0
  • Syntax
  add r10,r9,r8
  ; adds r8+r9 and stores in r10

ADD Immediate - Add Immediate to register[edit]

  • Add register to immediate and store in a register
  • The two registers can be any register (even the same register)
  • Sets the Condition Code Register bits
  • Syntax
  addi r10,r9,0x10  ; adds 0x10+r9 and stores in r10

SUBtract - Subtract two registers[edit]

  • Add two registers and store in a third
  • The three registers can be any register (even the same register)
  • Sets the Condition Code Register bits
  • Syntax
	lix		r10,7
	lix		r9,4
	sub		r8,r9,r10  ; r8 = r10 - r9
  • Result is 3

SUBtract Immediate - Subtract immediate from register[edit]

  • Subtract immediate from a register and store in a register
  • The two registers can be any register (even the same register)
  • Sets the Condition Code Register bits
  • Syntax
	lix		r10,7
	subi		r8,r9,0x4  ; r8 = r10 - 0x4
  • Result is 3

MULtiply - Multiply two registers[edit]

  • Multiplies two registers and store in a third
  • The three registers can be any register (even the same register)
  • Sets the Condition Code Register bits
  • Syntax
  mul r10,r9,r8
  ; multiplies r8 * r9 and stores in r10

MULtiply Immediate - Multiply register by an immediate[edit]

  • Multiplies immediate times a register and store in a register
  • The two registers can be any register (even the same register)
  • Sets the Condition Code Register bits
  • Syntax
  muli r9,r8,0x5
  ; multiplies r8 * 5 and stores in r9

CMP - CoMPare[edit]

  • Compares two registers but does not store the result
  • The two registers can be any register (even the same register)
  • Sets the Condition Code Register bits
  • Syntax
  cmp r8,r9
; compares r8 and r9 and sets condition code register bits

CMPI - CoMPare register and immediate[edit]

  cmpi r8,0x22  ; compares r8 and 0x22 and sets condition code register bits

OR - OR registers[edit]

  • Logical OR of two registers and store in a third
  • The three registers can be any register (even the same register)
  • Sets the Condition Code Register bits
  • Syntax
  or r10,r9,r8
  ; Logical bit-wise OR of r8 OR r9 and stores in r10

ORI - OR Immediate register to immediate[edit]

  • Logical OR of immediate and register and store in a register
  • The two registers can be any register (even the same register)
  • Sets the Condition Code Register bits
  • Syntax
  ori r9,r8,0x20   ; Logical bit-wise OR of r8 OR 0x20 and stores in r9

AND - AND registers[edit]

  • Logical AND of two registers and store in a third
  • The three registers can be any register (even the same register)
  • Sets the Condition Code Register bits
  • Syntax
  and r10,r9,r8
  ; Logical bit-wise AND of r8 AND r9 and stores in r10

ANDI - AND immediate and register[edit]

  • Logical AND of register and immediate and store in a register
  • The two registers can be any register (even the same register)
  • Sets the Condition Code Register bits
  • Syntax
  ando r9,r8,x0fe  ; Logical bit-wise AND of r8 AND 0xFE and stores in r9

XOR - eXclusive-or Registers[edit]

  • Logical Exclusive-OR of two registers and store in a third
  • The three registers can be any register (even the same register)
  • Sets the Condition Code Register bits
  • Syntax
  xor r10,r9,r8
  ; Logical bit-wise Exclusive-OR of r8 XOR r9 and stores in r10

XORI - eXclusive-or Register and immediate[edit]

  • Logical Exclusive-OR of two registers and store in a third
  • The three registers can be any register (even the same register)
  • Sets the Condition Code Register bits
  • Syntax
  xori r9,r9,0xFF  ; Logical bit-wise Exclusive-OR of r8 XOR 0xFF and stores in r9

SL1 - Shift Left by 1[edit]

  sl1 r9,r8
  ; shift r8 left by 1 bit and stores in r9

SL8 - Shift Left by 8 bits[edit]

  sl8 r9,r8
  ; shift r8 left by 8 bits and stores in r9

SR1 - Shift Right by 1[edit]

  sr1 r9,r8
  ; shift r8 right by 1 bit and stores in r9

SR8 - Shift Right by 8[edit]

  sr1 r9,r8
  ; shift r8 right by 8 bits and stores in r9

ROL1 - Rotate Left by 1[edit]

  rol1 r9,r8
  ; rotates r8 left by 1 bit and stores in r8

ROR1 - Rotate Right by 1[edit]

  ror1 r9,r8
  ; rotates r8 right by 1 bit and stores in r9

ASR - Arithmetic shift Right by 1[edit]

  • Shift register Right by 1 bit
  • Most significant bit is duplicated (allows for signed math)
  • Sets the Condition Code Register bits
  • Syntax
  asr r9,r8
  ; shift r8 right by 1 bit and stores in r9

ENS - ENdian Swap[edit]

  • Swaps the endian of a long register into a long register
    • d[31..24] > d[7..0]
    • d[23..16] > d[15..8]
    • d[15..8] > d[23..16]
    • d[7..0] > d[31..24]
  • Useful for taking byte data packed into the Data RAM and re-ordering it to write it out to a peripheral
  • Syntax
  ens r9,r8
  ; endian swap r8 and stores in r9

Immediate Operations[edit]

LIL - Load Immediate Lower[edit]

  • Takes the bottom 16-bits of the Instruction and puts it into the lower half of a register
    • Does not affect the upper half of the register
  • Syntax
  lil  r8,0x1234
  lil  dataLabel.lower

LIU - Load Immediate Upper[edit]

  • Takes the bottom 16-bits of the Instruction and puts it into the upper half of a register
    • Does not affect the lower half of the register
  • Syntax
  liu  r8,0x1234
  liu  dataLabel.upper

LIX - Load Immediate Extended[edit]

  • Takes the bottom 20-bits of the Instruction and puts it into the lower half of a register
  • Sign extends the most significant bit into the top 20-bits
  • Syntax
  lix  r8,0x12345  ; leaves r8 = 0x00012345

Load/Store Operations[edit]

  • Load from the Data Memory into a register
  • Store from a register into the Data Memory
  • DAR (Data Address Register) points to the Data Memory
  • Post increment forms add one, two or four to the DAR (for byte, short, long transfers)

LDB[P] - Load Data Byte[edit]

  • Load register from a Data space
  • Size is byte
  • [P] - increment the DAR after the operation
  • Syntax
  ldb  r8

SDB[P] - Store Data Byte[edit]

  • Store a register to the Data space
  • Size is byte
  • [P] - increment the DAR after the operation
  • Syntax
  sdb  r8

LDS[P] - Load Data Short[edit]

  • Load register from a Data space
  • Size is short (16-bits)
  • [P] - increment the DAR after the operation
  • Syntax
  lds  r8

SDS[P] - Store Data Short[edit]

  • Store a register to the Data space
  • Size is short (16-bits)
  • [P] - increment the DAR after the operation
  • Syntax
  sds  r8

LDL[P] - Load Data Long[edit]

  • Load register from a Data space
  • Size is long (32-bits)
  • [P] - increment the DAR after the operation
  • Syntax
  ldl  r8

SDL[P] - Store Data Long[edit]

  • Store a register to the Data space
  • Size is long (32-bits)
  • [P] - increment the DAR after the operation
  • Syntax
  sdl  r8

Peripheral Operations[edit]

  • Load from the Peripheral Space into a register
  • Store from a register into the Peripheral Space
  • PAR (Peripheral Address Register) points to the Peripheral Memory
  • Post increment forms add one, two or four to the DAR (for byte, short, long transfers)

LPB[P] - Load Peripheral Byte[edit]

  • Load a byte from a peripheral into a register
  • [P] - increment the DAR after the operation
  • Syntax
  lpb  r8

SPB[P] - Store Peripheral Byte[edit]

  • Store a register to a peripheral - byte sized
  • [P] - increment the DAR after the operation
  • Syntax
  spb  r8

LPS[P] - Load Peripheral Short[edit]

  • Load a short from a peripheral into a register
  • [P] - increment the DAR after the operation
  • Syntax
  lps  r8

SPS[P] - Store Peripheral Short[edit]

  • Store a register to a peripheral - short sized
  • [P] - increment the DAR after the operation
  • Syntax
  sps  r8

LPL[P] - Load Peripheral Long[edit]

  • Load a long from a peripheral into a register
  • [P] - increment the DAR after the operation
  • Syntax
  lpl  r8

SPL - Store Peripheral Long[edit]

  • Store a register to a peripheral - long sized
  • [P] - increment the DAR after the operation
  • Syntax
  spl  r8

Stack Operations[edit]

PSS - Push Stack[edit]

  • Push a register onto the stack
  • Stack grows up in addresses
  • Auto-increments the stack pointer after the push
  • Syntax
  pss  r8

PUS - Pull Stack[edit]

  • Pull a value from the stack
  • Pre-decrements the stack pointer
  • Syntax
  pus  r8

SSS - Store to Stack[edit]

  • Store a long register value to the address pointed to by the stack pointer
  • Doesn't auto-increment the stack pointer
  • Syntax
  sss  r8

LSS - Load from Stack[edit]

  • Load a long from the address pointed to be the stack pointer
  • Syntax
  lss  r8

Flow Control[edit]

BRA - Branch Always[edit]

  • Unconditionally branches to an address
    • Address is a signed 24-bit relative branch value
  • Syntax
  bra  label

BEZ - Branch Equal to Zero[edit]

  • Conditionally branches to an address if the CCR Equal to Zero bit is set
  • Address is a signed 24-bit relative branch value
  • Syntax
  beq  label

BE1 - Branch Equal to One[edit]

  • Conditionally branches to an address if the CCR Equal to One value bit is set
  • Address is a signed 24-bit relative branch value
  • Syntax
  be1  label

BNZ - Branch if Not Zero[edit]

  • Conditionally branches to an address if the CCR Not Zero value bit is set
  • Address is a signed 24-bit relative branch value
  • Syntax
  bnz  label

BCC - Branch if carry is clear[edit]

  • Conditionally branches to an address if the CCR Carry Clear bit is set to 1
  • Address is a signed 24-bit relative branch value
  • Syntax
  bcc  label

BCS - Branch if carry is set[edit]

  • Conditionally branches to an address if the CCR Carry Set bit is set to 1
  • Address is a signed 24-bit relative branch value
  • Syntax
  bcs  label

BLT - Branch Less Than[edit]

  • Conditionally branches to an address if the CCR Less Than bit is set
  • Address is a signed 24-bit relative branch value
  • Syntax
  blt  label

BGT - Branch Greater Than[edit]

  • Conditionally branches to an address if the CCR Greater Than bit is set
  • Address is a signed 24-bit relative branch value
  • Syntax
  bgt  label

BEQ - Branch Equal[edit]

  • Conditionally branches to an address if the CCR Equal bit is set
  • Address is a signed 24-bit relative branch value
  • Syntax
  beq  label

BNE - Branch Not Equal[edit]

  • Conditionally branches to an address if the CCR Not Equal bit is set
  • Address is a signed 24-bit relative branch value
  • Syntax
  bne  label

BSR - Branch Subroutine[edit]

  • Branches to a subroutine address
  • Address is a signed 24-bit relative branch value
  • Syntax
  bsr  label
  • To return form the subroutine, execute:
  pus  r7