Difference between revisions of "SIMPLE-68008"
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* 10 MHz clock | * 10 MHz clock | ||
* 512KB SRAM | * 512KB SRAM | ||
− | * Up to | + | * Up to 512KB EPROM/EEPROM |
* 68681 Dual Serial Port (ACIA) | * 68681 Dual Serial Port (ACIA) | ||
** Headers for FTDI | ** Headers for FTDI | ||
Line 19: | Line 19: | ||
* 0x80000-0x8FFFF Serial (ACIA) | * 0x80000-0x8FFFF Serial (ACIA) | ||
* 0x99000-0xFFFFF Up to 8KB EPROM | * 0x99000-0xFFFFF Up to 8KB EPROM | ||
+ | |||
+ | === Chip Set === | ||
+ | |||
+ | * [https://www.ebay.com/itm/113047590718 On Ebay] | ||
+ | |||
+ | [[file:EBAY_68000_SET.jpg]] | ||
+ | |||
+ | == Design == | ||
+ | |||
+ | * CPU | ||
+ | |||
+ | [[file:SIMPLE-68008_U5_CPU.PNG]] | ||
+ | |||
+ | * EPROM | ||
+ | |||
+ | [[file:SIMPLE-68008_U8_EPROM.PNG]] | ||
+ | |||
+ | * SRAM | ||
+ | |||
+ | [[file:SIMPLE-68008_U7_SRAM.PNG]] | ||
+ | |||
+ | * Dual UART | ||
+ | |||
+ | [[file:SIMPLE-68008_U6_DUART.PNG]] | ||
+ | |||
+ | * Reset | ||
+ | |||
+ | [[file:SIMPLE-68008_U4_RESET.PNG]] | ||
+ | |||
+ | * Clock | ||
+ | |||
+ | [[file:SIMPLE-68008_U1_OSC.PNG]] | ||
+ | |||
+ | * PLDs | ||
+ | |||
+ | [[file:SIMPLE-68008_U2_U3_PLDS.PNG]] | ||
+ | |||
+ | === PLDs === | ||
+ | |||
+ | <pre> | ||
+ | ==== PLD_001 ==== | ||
+ | |||
+ | Name SIMPLE-68008_PLD_1; | ||
+ | Partno ATF16V8B; | ||
+ | Date 09/14/22; | ||
+ | Revision 01; | ||
+ | Designer DOUG G; | ||
+ | Company LAND BOARDS LLC; | ||
+ | Assembly U02; | ||
+ | Location CONNELLSVILLE PA; | ||
+ | Device G16V8; | ||
+ | |||
+ | /* | ||
+ | */ | ||
+ | |||
+ | /* Inputs */ | ||
+ | PIN 1 = CLK; | ||
+ | PIN 2 = !CPUAS; | ||
+ | PIN 3 = !CPUDS; | ||
+ | PIN 4 = CPUA16; | ||
+ | PIN 5 = CPUA17; | ||
+ | PIN 6 = CPUA18; | ||
+ | PIN 7 = CPUA19; | ||
+ | PIN 8 = CPUFC0; | ||
+ | PIN 9 = CPUFC1; | ||
+ | PIN 11 = CPUFC2; | ||
+ | PIN 12 = !DDTACK; | ||
+ | PIN 13 = !SWAP; | ||
+ | |||
+ | /* Outputs */ | ||
+ | PIN 14 = !CPUIACK; | ||
+ | PIN 15 = !DUARTCS; | ||
+ | PIN 16 = !CPUDTACK; | ||
+ | PIN 17 = WAIT1; | ||
+ | PIN 18 = !RAMSEL; | ||
+ | PIN 19 = WAIT2; | ||
+ | |||
+ | CPUIACK = CPUFC2 & CPUFC1 & CPUFC0; | ||
+ | |||
+ | DUARTCS = CPUA19 & !CPUA18 & !CPUA17 & !CPUA16 & CPUDS; | ||
+ | |||
+ | RAMSEL = !CPUA19 & SWAP & CPUDS; | ||
+ | |||
+ | CPUDTACK = CPUA19 & !CPUA18 & !CPUA17 & !CPUA16 & CPUDS & !DDTACK | ||
+ | # CPUA19 & CPUA18 & CPUDS | ||
+ | # CPUA19 & CPUA17 & CPUDS | ||
+ | # CPUA19 & CPUA16 & CPUDS | ||
+ | # !CPUA19 & CPUDS; | ||
+ | </pre> | ||
+ | |||
+ | |||
+ | ==== PLD_002 ==== | ||
+ | |||
+ | <pre> | ||
+ | Name SIMPLE-68008_PLD_2; | ||
+ | Partno ATF16V8B; | ||
+ | Date 09/14/22; | ||
+ | Revision 01; | ||
+ | Designer DOUG G; | ||
+ | Company LAND BOARDS LLC; | ||
+ | Assembly U03; | ||
+ | Location CONNELLSVILLE, PA; | ||
+ | Device G16V8; | ||
+ | |||
+ | /* | ||
+ | RESET CONTROLLER, ROM CHIP SELECT | ||
+ | */ | ||
+ | |||
+ | /* Inputs */ | ||
+ | PIN 1 = CLK; | ||
+ | PIN 2 = !CPUWR; | ||
+ | PIN 3 = !CPUDS; | ||
+ | PIN 4 = CPUA16; | ||
+ | PIN 5 = CPUA17; | ||
+ | PIN 6 = CPUA18; | ||
+ | PIN 7 = CPUA19; | ||
+ | PIN 8 = !POR; | ||
+ | PIN 9 = CPUD0; | ||
+ | |||
+ | /* Outputs */ | ||
+ | PIN 14 = SWAP; | ||
+ | PIN 15 = !ROMCS; | ||
+ | PIN 16 = !MEMRD; | ||
+ | PIN 18 = !CPUHLT; | ||
+ | PIN 19 = !CPURES; | ||
+ | |||
+ | /* CLEAR SWAP AT POWER UP, RESET */ | ||
+ | /* SET SWAP BY FIRST WRITE TO EPROM SPACE */ | ||
+ | SWAP.D = CPUDS & CPUWR & CPUA19 & CPUA18 & CPUA17 & CPUA16 & CPUD0 & !POR | ||
+ | # SWAP & !POR; | ||
+ | |||
+ | ROMCS = CPUDS & !CPUWR & CPUA19 & CPUA18 | ||
+ | # CPUDS & !CPUWR & CPUA19 & CPUA17 | ||
+ | # CPUDS & !CPUWR & CPUA19 & CPUA16 | ||
+ | # CPUDS & !CPUA19 & !CPUA18 & !CPUA17 & !CPUA16 & !SWAP; | ||
+ | |||
+ | CPUHLT_N.OE = POR; | ||
+ | CPUHLT_N = POR; | ||
+ | |||
+ | CPURES_N.OE = POR; | ||
+ | CPURES_N = POR; | ||
+ | </pre> | ||
== Headers / Connectors == | == Headers / Connectors == | ||
Line 415: | Line 557: | ||
== Software == | == Software == | ||
+ | |||
+ | * Run [https://github.com/douggilliland/Retro-Computers/tree/master/68000/TS2_FPGA/Tutor TUTOR 1.2 Monitor] | ||
== Mechanicals == | == Mechanicals == |
Latest revision as of 20:31, 3 March 2023
Contents
Features
- 68008 CPU
- 10 MHz clock
- 512KB SRAM
- Up to 512KB EPROM/EEPROM
- 68681 Dual Serial Port (ACIA)
- Headers for FTDI
- 38,400 baud
- Reset switch with optional Power Supervisor
- 95x95mm card
- (4) 6-32 mounting holes
Memory Map
- 0x00000-0x7FFFF 32KB SRAM
- 0x80000-0x8FFFF Serial (ACIA)
- 0x99000-0xFFFFF Up to 8KB EPROM
Chip Set
Design
- CPU
- EPROM
- SRAM
- Dual UART
- Reset
- Clock
- PLDs
PLDs
==== PLD_001 ==== Name SIMPLE-68008_PLD_1; Partno ATF16V8B; Date 09/14/22; Revision 01; Designer DOUG G; Company LAND BOARDS LLC; Assembly U02; Location CONNELLSVILLE PA; Device G16V8; /* */ /* Inputs */ PIN 1 = CLK; PIN 2 = !CPUAS; PIN 3 = !CPUDS; PIN 4 = CPUA16; PIN 5 = CPUA17; PIN 6 = CPUA18; PIN 7 = CPUA19; PIN 8 = CPUFC0; PIN 9 = CPUFC1; PIN 11 = CPUFC2; PIN 12 = !DDTACK; PIN 13 = !SWAP; /* Outputs */ PIN 14 = !CPUIACK; PIN 15 = !DUARTCS; PIN 16 = !CPUDTACK; PIN 17 = WAIT1; PIN 18 = !RAMSEL; PIN 19 = WAIT2; CPUIACK = CPUFC2 & CPUFC1 & CPUFC0; DUARTCS = CPUA19 & !CPUA18 & !CPUA17 & !CPUA16 & CPUDS; RAMSEL = !CPUA19 & SWAP & CPUDS; CPUDTACK = CPUA19 & !CPUA18 & !CPUA17 & !CPUA16 & CPUDS & !DDTACK # CPUA19 & CPUA18 & CPUDS # CPUA19 & CPUA17 & CPUDS # CPUA19 & CPUA16 & CPUDS # !CPUA19 & CPUDS;
PLD_002
Name SIMPLE-68008_PLD_2; Partno ATF16V8B; Date 09/14/22; Revision 01; Designer DOUG G; Company LAND BOARDS LLC; Assembly U03; Location CONNELLSVILLE, PA; Device G16V8; /* RESET CONTROLLER, ROM CHIP SELECT */ /* Inputs */ PIN 1 = CLK; PIN 2 = !CPUWR; PIN 3 = !CPUDS; PIN 4 = CPUA16; PIN 5 = CPUA17; PIN 6 = CPUA18; PIN 7 = CPUA19; PIN 8 = !POR; PIN 9 = CPUD0; /* Outputs */ PIN 14 = SWAP; PIN 15 = !ROMCS; PIN 16 = !MEMRD; PIN 18 = !CPUHLT; PIN 19 = !CPURES; /* CLEAR SWAP AT POWER UP, RESET */ /* SET SWAP BY FIRST WRITE TO EPROM SPACE */ SWAP.D = CPUDS & CPUWR & CPUA19 & CPUA18 & CPUA17 & CPUA16 & CPUD0 & !POR # SWAP & !POR; ROMCS = CPUDS & !CPUWR & CPUA19 & CPUA18 # CPUDS & !CPUWR & CPUA19 & CPUA17 # CPUDS & !CPUWR & CPUA19 & CPUA16 # CPUDS & !CPUA19 & !CPUA18 & !CPUA17 & !CPUA16 & !SWAP; CPUHLT_N.OE = POR; CPUHLT_N = POR; CPURES_N.OE = POR; CPURES_N = POR;
Headers / Connectors
J1 - 2 port FTDI / TTL Serial
- 2x6 header
- Direct connect to DTE RS-232 card
- Flip order to connect to USB to TTL Serial (FTDI)
- TX<>RX
- RTS<>CTS
- Pinout
- GND
- CTS* (in)
- +5V
- Transmit (out)
- Receive (in)
- RTS* (out)
J2 - Input Port
- Input 2
- Input 5
- Input 4
- Input 3
- Vcc
- GND
J3 - Output Port
- GND
- Vcc
- Output 7
- Output 6
- Output 5
- Output 4
- Output 3
- Output 2
H1 - 5V Power
- 2x4 header
H3-H5 - EPROM/EEPROM Select Jumpers
- H2 = EE PIN 31
- H3 = EE PIN 3
- H4 = EE PIN 30
- H5 = EE PIN 29
27040 | 27020 | 27010 | 27512 | 27256 | 27128 | 2764 | PIN(32) | PIN(28) | PIN(28) | PIN(32) | 2764 | 27128 | 27256 | 27512 | 27010 | 27020 | 27040 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
VPP | VPP | VPP | N/A | N/A | N/A | N/A | 1 | N/A | N/A | 32 | N/A | N/A | N/A | N/A | VCC | VCC | VCC | |
A16 | A16 | A16 | N/A | N/A | N/A | N/A | 2 | N/A | N/A | 31 (H2) | N/A | N/A | N/A | N/A | PGM | PGM | A18 | |
A15 | A15 | A15 | A15 | VPP | VPP | VPP | 3 (H3) | 1 | 28 | 30 (H4) | VCC | VCC | VCC | VCC | N/C | A17 | A17 | |
A12 | A12 | A12 | A12 | A12 | A12 | A12 | 4 | 2 | 27 | 29 (H5) | PGM | PGM | A14 | A14 | A14 | A14 | A14 | |
A7 | A7 | A7 | A7 | A7 | A7 | A7 | 5 | 3 | 26 | 28 | A13 | A13 | A13 | A13 | A13 | A13 | A13 | |
A6 | A6 | A6 | A6 | A6 | A6 | A6 | 6 | 4 | 25 | 27 | A8 | A8 | A8 | A8 | A8 | A8 | A8 | |
A5 | A5 | A5 | A5 | A5 | A5 | A5 | 7 | 5 | 24 | 26 | A9 | A9 | A9 | A9 | A9 | A9 | A9 | |
A4 | A4 | A4 | A4 | A4 | A4 | A4 | 8 | 6 | 23 | 25 | A11 | A11 | A11 | A11 | A11 | A11 | A11 | |
A3 | A3 | A3 | A3 | A3 | A3 | A3 | 9 | 7 | 22 | 24 | OE* | OE* | OE* | OE* | OE* | OE* | OE* | |
A2 | A2 | A2 | A2 | A2 | A2 | A2 | 10 | 8 | 21 | 23 | A10 | A10 | A10 | A10 | A10 | A10 | A10 | |
A1 | A1 | A1 | A1 | A1 | A1 | A1 | 11 | 9 | 20 | 22 | CE* | CE* | CE* | CE* | CE* | CE* | CE* | |
A0 | A0 | A0 | A0 | A0 | A0 | A0 | 12 | 10 | 19 | 21 | D7 | D7 | D7 | D7 | D7 | D7 | D7 | |
D0 | D0 | D0 | D0 | D0 | D0 | D0 | 13 | 11 | 18 | 20 | D6 | D6 | D6 | D6 | D6 | D6 | D6 | |
D1 | D1 | D1 | D1 | D1 | D1 | D1 | 14 | 12 | 17 | 19 | D5 | D5 | D5 | D5 | D5 | D5 | D5 | |
D2 | D2 | D2 | D2 | D2 | D2 | D2 | 15 | 13 | 16 | 18 | D4 | D4 | D4 | D4 | D4 | D4 | D4 | |
GND | GND | GND | GND | GND | GND | GND | 16 | 14 | 15 | 17 | D3 | D3 | D3 | D3 | D3 | D3 | D3 |