Difference between revisions of "R32V2020 32-bit RISC CPU Design"
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= Details = | = Details = | ||
| − | * [[Architecture]] - R32V2020 architecture. | + | * [[R32V2020 Architecture]] - R32V2020 architecture. |
| − | * [[Instruction Set]] | + | * [[R32V2020 Instruction Set]] |
** [https://github.com/douggilliland/R32V2020/blob/master/Assembler/R32V2020_Reference_Card.pdf Programmer's Reference Card] | ** [https://github.com/douggilliland/R32V2020/blob/master/Assembler/R32V2020_Reference_Card.pdf Programmer's Reference Card] | ||
| − | * [[Target Hardware]] - FPGA Resource Requirements | + | * [[R32V2020 Target Hardware]] - FPGA Resource Requirements |
| − | ** [[Resource requirements]] | + | ** [[R32V2020 Resource requirements]] |
| − | ** [[Porting to other FPGAs|Porting R32V2020 to other FPGAs]]. | + | ** [[R32V2020 Porting to other FPGAs|Porting R32V2020 to other FPGAs]]. |
| − | * [[Peripheral Interfaces]] - Peripheral IP that was developed under [http://searle.hostei.com/grant/Multicomp/index.html Multicomp project], [https://github.com/mvvproject/ReVerSE-U16 ReVerSE-16 project] and other projects. | + | * [[R32V2020 Peripheral Interfaces]] - Peripheral IP that was developed under [http://searle.hostei.com/grant/Multicomp/index.html Multicomp project], [https://github.com/mvvproject/ReVerSE-U16 ReVerSE-16 project] and other projects. |
| − | * [[Software Support]] - R32V2020 Software Support document(s). | + | * [[R32V2020 Software Support]] - R32V2020 Software Support document(s). |
| − | ** [[Assembler]] | + | ** [[R32V2020 Assembler]] |
| − | ** [[C Compiler]] | + | ** [[R32V2020 C Compiler]] |
| − | * [[Adding an Instruction to the ISA]] | + | * [[R32V2020 Adding an Instruction to the ISA]] |
| − | * [[Performance]] | + | * [[R32V2020 Performance]] |
| − | * [[Micro-Code]] | + | * [[R32V2020 Micro-Code]] |
| − | * [[Debug and Troubleshooting]] | + | * [[R32V2020 Debug and Troubleshooting]] |
* [https://www.youtube.com/watch?v=YuXSBQsL4EQ&list=PLn__0BqzWEWPIsUE0TUdsspej2vHV-osY R32V2020 Video Playlist] | * [https://www.youtube.com/watch?v=YuXSBQsL4EQ&list=PLn__0BqzWEWPIsUE0TUdsspej2vHV-osY R32V2020 Video Playlist] | ||
Revision as of 12:15, 10 April 2022
R32V2020 - 32-Bit RISC
- R32V2020 is a 32-bit RISC CPU.
- R32V2020 runs at 12.5 MIPS with a 50 MHz clock (4 clocks per instruction).
- R32V2020 is written in VHDL.
- R32V2020 is intended to be implemented in an FPGA.
- R32V2020 is a non-Von Neumann architecture so it may be unfamiliar at first glance.
- Attempts to avoid the Von Neumann bottleneck by having a separate instruction memory space
Details
- R32V2020 Architecture - R32V2020 architecture.
- R32V2020 Instruction Set
- R32V2020 Target Hardware - FPGA Resource Requirements
- R32V2020 Peripheral Interfaces - Peripheral IP that was developed under Multicomp project, ReVerSE-16 project and other projects.
- R32V2020 Software Support - R32V2020 Software Support document(s).
- R32V2020 Adding an Instruction to the ISA
- R32V2020 Performance
- R32V2020 Micro-Code
- R32V2020 Debug and Troubleshooting
- R32V2020 Video Playlist
Ownership
- We all stand on the shoulders of giants.
- Grant Searle's Multicomp project.
- Neil Crook's improvements to Multicomp.
- The concepts in this RISC design are found in any Computer Architecture Design textbook.
- Nice slideshow on another FPGA RISC design
Warning
- No warranty expressed or implied.
