Difference between revisions of "R32V2020 32-bit RISC CPU Design"
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| − | * 32-bit RISC CPU | + | = R32V2020 - 32-Bit RISC = |
| − | * [https://github.com/douggilliland/R32V2020 Land Boards R32V2020] | + | |
| − | * [https://github.com/douggilliland/R32V2020/ | + | * R32V2020 is a 32-bit RISC CPU |
| − | * [https://github.com/ | + | * R32V2020 runs at 12.5 MIPS with a 50 MHz clock (4 clocks per instruction) |
| + | * R32V2020 is [[Why VHDL for the R32V2020|written in VHDL]] | ||
| + | * R32V2020 is intended to be [[R32V2020 Target Hardware|implemented in an FPGA]] | ||
| + | * R32V2020 is a '''non-'''[https://en.wikipedia.org/wiki/Von_Neumann_architecture Von Neumann architecture] so it may be unfamiliar at first glance. | ||
| + | ** Attempts to avoid the [https://web.archive.org/web/20131212205159/http://aws.linnbenton.edu/cs271c/markgrj/ Von Neumann bottleneck] by having a separate instruction memory space | ||
| + | * [https://github.com/douggilliland/R32V2020 Land Boards R32V2020] - GitHub | ||
| + | |||
| + | == Videos == | ||
| + | |||
| + | * Part 1 of a [https://www.youtube.com/watch?v=YuXSBQsL4EQ&list=PLn__0BqzWEWPIsUE0TUdsspej2vHV-osY 33 part video series] | ||
| + | |||
| + | <video type="youtube">YuXSBQsL4EQ</video> | ||
| + | |||
| + | = Details = | ||
| + | |||
| + | * [[R32V2020 Architecture|Architecture]] - R32V2020 architecture. | ||
| + | * [[R32V2020 Instruction Set|Instruction Set]] | ||
| + | ** [https://github.com/douggilliland/R32V2020/blob/master/Assembler/R32V2020_Reference_Card.pdf Programmer's Reference Card] | ||
| + | * [[R32V2020 Target Hardware|Target Hardware]] - FPGA Resource Requirements | ||
| + | ** [[R32V2020 Resource requirements|Resource requirements]] | ||
| + | ** [[R32V2020 Porting to other FPGAs|Porting R32V2020 to other FPGAs]]. | ||
| + | * [[R32V2020 Peripheral Interfaces|Peripheral Interfaces]] - Peripheral IP that was developed under [http://searle.hostei.com/grant/Multicomp/index.html Multicomp project], [https://github.com/mvvproject/ReVerSE-U16 ReVerSE-16 project] and other projects. | ||
| + | * [[R32V2020 Software Support|Software Support]] - R32V2020 Software Support document(s). | ||
| + | ** [[R32V2020 Assembler|Assembler]] | ||
| + | ** [[R32V2020 C Compiler|C Compiler]] | ||
| + | * [[R32V2020 Adding an Instruction to the ISA|Adding an Instruction to the ISA]] | ||
| + | * [[R32V2020 Performance|Performance]] | ||
| + | * [[R32V2020 Micro-Code|Micro-Code]] | ||
| + | * [[R32V2020 Debug and Troubleshooting|Debug and Troubleshooting]] | ||
| + | |||
| + | = Ownership = | ||
| + | |||
| + | * We all stand on the shoulders of giants. | ||
| + | ** Grant Searle's [http://searle.hostei.com/grant/Multicomp/index.html Multicomp project]. | ||
| + | ** Neil Crook's [https://github.com/nealcrook/multicomp6809 improvements to Multicomp]. | ||
| + | * The concepts in this RISC design are found in any Computer Architecture Design textbook. | ||
| + | * [http://www.fpgacpu.org/papers/soc-gr0040-slides.pdf Nice slideshow on another FPGA RISC design] | ||
| + | |||
| + | = Warning = | ||
| + | |||
| + | * No warranty expressed or implied. | ||
Latest revision as of 13:17, 10 April 2022
R32V2020 - 32-Bit RISC
- R32V2020 is a 32-bit RISC CPU
- R32V2020 runs at 12.5 MIPS with a 50 MHz clock (4 clocks per instruction)
- R32V2020 is written in VHDL
- R32V2020 is intended to be implemented in an FPGA
- R32V2020 is a non-Von Neumann architecture so it may be unfamiliar at first glance.
- Attempts to avoid the Von Neumann bottleneck by having a separate instruction memory space
- Land Boards R32V2020 - GitHub
Videos
- Part 1 of a 33 part video series
Details
- Architecture - R32V2020 architecture.
- Instruction Set
- Target Hardware - FPGA Resource Requirements
- Peripheral Interfaces - Peripheral IP that was developed under Multicomp project, ReVerSE-16 project and other projects.
- Software Support - R32V2020 Software Support document(s).
- Adding an Instruction to the ISA
- Performance
- Micro-Code
- Debug and Troubleshooting
Ownership
- We all stand on the shoulders of giants.
- Grant Searle's Multicomp project.
- Neil Crook's improvements to Multicomp.
- The concepts in this RISC design are found in any Computer Architecture Design textbook.
- Nice slideshow on another FPGA RISC design
Warning
- No warranty expressed or implied.
