Difference between revisions of "R32V2020 32-bit RISC CPU Design"
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* R32V2020 runs at 12.5 MIPS with a 50 MHz clock (4 clocks per instruction) | * R32V2020 runs at 12.5 MIPS with a 50 MHz clock (4 clocks per instruction) | ||
* R32V2020 is [[Why VHDL for the R32V2020|written in VHDL]] | * R32V2020 is [[Why VHDL for the R32V2020|written in VHDL]] | ||
| + | * R32V2020 is intended to be [[R32V2020 Target Hardware|implemented in an FPGA]] | ||
* R32V2020 is intended to be [[Target Hardware|implemented in an FPGA]] | * R32V2020 is intended to be [[Target Hardware|implemented in an FPGA]] | ||
* R32V2020 is a '''non-'''[https://en.wikipedia.org/wiki/Von_Neumann_architecture Von Neumann architecture] so it may be unfamiliar at first glance. | * R32V2020 is a '''non-'''[https://en.wikipedia.org/wiki/Von_Neumann_architecture Von Neumann architecture] so it may be unfamiliar at first glance. | ||
Revision as of 13:07, 10 April 2022
R32V2020 - 32-Bit RISC
- R32V2020 is a 32-bit RISC CPU
- R32V2020 runs at 12.5 MIPS with a 50 MHz clock (4 clocks per instruction)
- R32V2020 is written in VHDL
- R32V2020 is intended to be implemented in an FPGA
- R32V2020 is intended to be implemented in an FPGA
- R32V2020 is a non-Von Neumann architecture so it may be unfamiliar at first glance.
- Attempts to avoid the Von Neumann bottleneck by having a separate instruction memory space
- Land Boards R32V2020 - GitHub
Details
- R32V2020 Architecture - R32V2020 architecture.
- R32V2020 Instruction Set
- R32V2020 Target Hardware - FPGA Resource Requirements
- R32V2020 Peripheral Interfaces - Peripheral IP that was developed under Multicomp project, ReVerSE-16 project and other projects.
- R32V2020 Software Support - R32V2020 Software Support document(s).
- R32V2020 Adding an Instruction to the ISA
- R32V2020 Performance
- R32V2020 Micro-Code
- R32V2020 Debug and Troubleshooting
- R32V2020 Video Playlist
Ownership
- We all stand on the shoulders of giants.
- Grant Searle's Multicomp project.
- Neil Crook's improvements to Multicomp.
- The concepts in this RISC design are found in any Computer Architecture Design textbook.
- Nice slideshow on another FPGA RISC design
Warning
- No warranty expressed or implied.
