R32V2020 32-bit RISC CPU Design

R32V2020 - 32-Bit RISC

• R32V2020 is a 32-bit RISC CPU
• R32V2020 runs at 12.5 MIPS with a 50 MHz clock (4 clocks per instruction)
• R32V2020 is written in VHDL
• R32V2020 is intended to be implemented in an FPGA
• R32V2020 is a non-Von Neumann architecture so it may be unfamiliar at first glance.
  • Attempts to avoid the Von Neumann bottleneck by having a separate instruction memory space
• Land Boards R32V2020 - GitHub

Videos

• Part 1 of a many part series

Details

• R32V2020 Architecture - R32V2020 architecture.
• R32V2020 Instruction Set
  • Programmer's Reference Card
• R32V2020 Target Hardware - FPGA Resource Requirements
  • R32V2020 Resource requirements
  • Porting R32V2020 to other FPGAs.
• R32V2020 Peripheral Interfaces - Peripheral IP that was developed under Multicomp project, ReVerSE-16 project and other projects.
• R32V2020 Software Support - R32V2020 Software Support document(s).
  • R32V2020 Assembler
  • R32V2020 C Compiler
• R32V2020 Adding an Instruction to the ISA
• R32V2020 Performance
• R32V2020 Micro-Code
• R32V2020 Debug and Troubleshooting
• R32V2020 Video Playlist

Ownership

• We all stand on the shoulders of giants.
  • Grant Searle's Multicomp project.
  • Neil Crook's improvements to Multicomp.
• The concepts in this RISC design are found in any Computer Architecture Design textbook.
• Nice slideshow on another FPGA RISC design

Warning

• No warranty expressed or implied.