Difference between revisions of "R32V2020 Architecture"
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* Four physically separate Memory Spaces for Instruction, Data, Stack and Peripherals | * Four physically separate Memory Spaces for Instruction, Data, Stack and Peripherals | ||
Latest revision as of 13:25, 10 April 2022
Architectural Overview
- Four physically separate Memory Spaces for Instruction, Data, Stack and Peripherals
- 32-bits of data and address for Instruction, Data and Stack
- Peripheral space can be byte-word-long values
- Small Opcode set
- Register File
- Arithmetic Logic Unit (ALU)
- Flow control
- Timing Controller
- Instruction Pipeline
- Big vs Little Endian
Ownership
- We all build on the shoulders of giants.
Warning
- No warranty is expressed or implied.
