R32V2020 Architecture

Architectural Overview

• Four physically separate Memory Spaces for Instruction, Data, Stack and Peripherals
  • Instruction Space
  • Data Space
  • Stack Space
  • Peripheral (I/O) Space
• 32-bits of data and address for Instruction, Data and Stack
• Peripheral space can be byte-word-long values
• Small Opcode set
• Register File
  • Condition Code Register
• Arithmetic Logic Unit (ALU)
  • ALU Arithmetic operations
  • ALU Logical operations
  • Shift/Rotate operations
• Flow control
• Timing Controller
• Instruction Pipeline
• Big vs Little Endian

Ownership

• We all build on the shoulders of giants.

Warning

• No warranty is expressed or implied.